For years, the server CPU was the quiet workhorse of the data center — important, but rarely the headline. AI changed that. On November 10, 2026, AMD made the CPU a headline again, announcing general availability of its 6th Gen AMD EPYC server processors, code-named Venice. Built on the new Zen 6 architecture and a 2nm-class manufacturing process, the lineup tops out at 256 cores and 512 threads per socket, and AMD is pitching it squarely at the workloads AI agents create.
Systems powered by the new chips are already shipping from leading server vendors, and cloud instances from Microsoft Azure and Oracle Cloud Infrastructure are on the way. It is the biggest server CPU launch of the year — and a direct challenge to Nvidia and Intel in the race to power agentic AI.
What AMD Announced on November 10
AMD announced the general availability of the 6th Gen AMD EPYC SP7 processors on November 10, 2026. The chips are based on the new Zen 6 architecture and are manufactured on TSMC’s latest two-nanometer-class process node, the first such node built on gate-all-around transistor technology.
The launch covers 10 processors organized into two groups: high-frequency chips with fewer, faster cores, and high-density chips with a large number of slower cores. The idea is that different data center jobs need different CPUs — a database or a GPU host node wants clock speed, while a fleet of AI agent sandboxes wants core count. AMD’s bet is that one architecture, tuned two ways, can cover both.
“AI is significantly expanding the role of the CPU across every layer of the data center,” said Dan McNamara, AMD’s senior vice president and general manager of Compute and Enterprise AI. “With 6th Gen AMD EPYC, customers can standardize on the proven x86 foundation while choosing a workload-optimized solution to run more agents, keep accelerated infrastructure fed and power the business-critical applications they depend on.”
AMD CEO Lisa Su made the same point to analysts last week, saying agents “are quickly becoming the next killer app for CPUs in the cloud” — and that early demand for Venice is the strongest AMD has seen for any new EPYC generation.
Zen 6: Two Cores, One Architecture
The Zen 6 architecture ships in two editions. Standard Zen 6 cores are optimized for clock speed, while the scaled-down Zen 6c cores are designed for maximum core density. According to SiliconANGLE’s launch coverage, the architecture delivers 31% higher instructions per clock (IPC) than AMD’s previous design when running AI workloads, an increase AMD attributes partly to the move to TSMC’s two-nanometer node.
The density gains are substantial. Standard Zen 6 compute dies now scale to 12 cores with 48 MB of shared L3 cache, up from 8 cores in Zen 5. The Zen 6c dies double to 32 cores with 128 MB of L3 cache — four times the cache of the previous generation’s density cores. Zen 6 also adds native FP16 half-precision support and improved VNNI-INT8 instructions, which condense multiple AI calculations into a single operation.
The platform moves to the new SP7 socket with 16 memory channels, supporting DDR5-8000 and MRDIMM-12800 memory at up to 1.6 terabytes per second per socket, alongside PCIe 6.0 — the first x86 server platform with the new interconnect standard.
The Numbers That Matter
The headline figures from the launch:
- Up to 256 cores and 512 threads per socket. The densest EPYC 6 chips run at a 2.55 GHz base clock, with each core powering two threads — enough to run a large fleet of AI agents on a single socket.
- Up to 5.3 GHz boost. The two highest-frequency chips pack 96 cores with a 384 MB cache, a 4.05 GHz base clock, and a 5.3 GHz boost for demanding workloads.
- Up to 3.7x the performance of Nvidia Vera. AMD says a system built on its flagship EPYC 9996 delivers up to 3.7 times the performance of a Vera-based system, and up to 2.2 times the performance — with 2.0 times the performance per dollar — of an Intel Xeon 6980P system. These are vendor figures, not independent tests.
- Up to 3.3x more agents per watt. For agent sandboxes, AMD claims its high-density chips support up to about 3.3 times as many agents per CPU watt as Nvidia Vera, and about 2.5 times as many as Intel Xeon 6980P.
- 93% generational gain. In SPEC CPU 2026 throughput testing, a dual EPYC 9996 configuration delivered a 93% performance gain over the previous generation’s dual EPYC 9965, according to independent testing reported at launch.
The competitive framing is deliberate: AMD is not selling Venice as a general-purpose refresh. It is selling it as the CPU for the agentic era, measured in agents per watt and agents per rack rather than raw gigahertz alone.
Built for AI Agents, Not Just Servers
Why does a CPU launch revolve around AI agents? Because agents split their work. The neural network itself runs on GPUs, but everything around it — the tools agents call, the databases they query, the code they execute, the sandboxes they run in — runs on CPUs. A single complex task can spin up hundreds of agents, each needing its own isolated sandbox, and those sandboxes need cores.
AMD maps the EPYC 6 portfolio to three distinct CPU roles in agentic infrastructure: general-purpose services, GPU host nodes, and agent sandboxes. High-frequency host-node processors running at up to 5.3 GHz can deliver up to 1.8 times the large language model output throughput of previous-generation EPYC chips, while the high-density parts host the sandboxes. Within the same 35-kilowatt power envelope, AMD estimates EPYC 9996-based servers can support about 1.18 times as many agents per rack as competing systems.
There is also a cost angle that matters to enterprises. Some business software, notably databases, is licensed per core — so running a database on fewer, faster cores can be cheaper than spreading it across many slower ones. That is exactly what the high-frequency EPYC 6 chips are for, and it is why the lineup’s split personality is a feature rather than a compromise.
This agent-first design thinking is showing up across the industry. Google’s Gemini 4 Carbon, now generally available, is built for long-horizon agentic work, while open-weight models such as Mistral Large 4 and simulation platforms like NVIDIA’s Cosmos 3 world models are expanding what agents can do. Venice is the hardware side of the same shift: the infrastructure that lets those agents run at scale.
From Servers to Rack-Scale AI: AMD Helion
Venice does not stop at the server. AMD is extending the platform to its Helion agentic AI racks, an open blueprint introduced in October 2026, with three configurations: Helion Liquid for maximum agent density alongside AMD’s Helios rack-scale systems, Helion Air for expanding capacity inside existing air-cooled data centers, and Helion Air Inference, which combines CPU execution with local GPU inference in a single rack.
The densest Helion configurations reach up to 73,728 threads in a single rack — the most agents AMD says any rack can deliver. Customers can choose the balance of CPU and GPU capacity, cooling, and connectivity that fits their infrastructure as agent demand grows.
Ecosystem Support and Availability
Systems powered by 6th Gen EPYC processors are shipping now from leading server vendors, with more than 240 platforms committed — about 20% more than for the previous Turin generation. Meta is working with AMD as a lead customer and has been validating the new platforms ahead of deployment at scale.
On the cloud side, Microsoft Azure is bringing 6th Gen EPYC to customers across its AI infrastructure stack, with Azure HDv2 instances now in preview for AI data processing, agentic AI and high-performance computing, plus Azure HXv2 for chip design and technical computing. Oracle Cloud Infrastructure’s Compute E7 instances will also be powered by the new chips, supporting enterprise applications and the CPU services around AI models. AMD says the chips are expected to power cloud instances across all major global cloud providers.
More variants are already on the roadmap: the SP8 platform is expected early next year, followed by Venice-X with 3D V-Cache and low-power LPDDR5X versions in 2027. For now, though, the SP7 family is the one shipping — and the one data centers will be measured against.
What It Means for the Data Center
The EPYC 6 launch is a reminder that the AI boom is not only a GPU story. As agents move from demos to production, the unglamorous work of running their tools, sandboxes, and databases falls to CPUs — and AMD wants those CPUs to be Venice. With up to 256 cores per socket, a 5.3 GHz boost, PCIe 6.0, and claims of up to 3.3 times the agents per watt of its nearest rival, the chip makes a strong opening case.
The real test will be independent benchmarks and cloud pricing once Azure and OCI instances go live. But one thing is already clear: the CPU is back at the center of the data center conversation. And the same AMD silicon that powers the classical side of IBM, Oak Ridge and AMD’s quantum error-correction platform is now being asked to power the agentic era too — a sign of how far the humble server processor has come.
